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PM7380-PI 参数 Datasheet PDF下载

PM7380-PI图片预览
型号: PM7380-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 帧引擎和数据链路管理32P672 [FRAME ENGINE AND DATA LINK MANAGER 32P672]
分类和应用:
文件页数/大小: 332 页 / 2479 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM7380 FREEDM-32P672  
DATA SHEET  
PMC-1990262  
ISSUE 5  
FRAME ENGINE AND DATA LINK MANAGER 32P672  
Register 0x480 – 0x488 : TCAS Links #0 to #2 Configuration  
Bit  
Type  
Function  
Default  
Bit 31  
Unused  
XXXXXXXH  
to  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
R/W  
BSYNC  
Unused  
MODE[2]  
MODE[1]  
MODE[0]  
0
X
0
0
0
R/W  
R/W  
R/W  
This register configures operational modes of transmit links #0 to #2.  
Note  
This register is not byte addressable. Writing to this register modifies all the bits  
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not  
implemented. However, when all four byte enables are negated, no access is  
made to this register.  
MODE[2:0]:  
The mode select bits (MODE[2:0]) configures the corresponding transmit link.  
Table 27 details this procedure. When link 4m (0?m?7) is configured for  
operation in 8.192 Mbps H-MVIP mode, links 4m+1, 4m+2 and 4m+3 are  
driven with constant ones. However, links 4m+1, 4m+2 and 4m+3 must be  
configured for 8.192 Mbps H-MVIP mode for correct operation of the  
TCAS672. From a channel assignment point of view in the TCAS672  
(Registers 0x100, 0x104), time-slots 0 through 31 of link 4m are mapped to  
time-slots 0 through 31 of the H-MVIP link, time-slots 0 through 31 of link  
4m+1 are mapped to time-slots 32 through 63 of the H-MVIP link, time-slots 0  
through 31 of link 4m+2 are mapped to time-slots 64 through 95 of the H-  
MVIP link and time-slots 0 through 31 of link 4m+3 are mapped to time-slots  
96 through 127 of the H-MVIP link.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
238  
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