RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
XFER[3:0]:
The indirect channel transfer size (XFER[3:0]) specifies the amount of data
the partial packet processor requests from the TMAC672 block. The channel
transfer size to be written to the channel provision RAM, in an indirect write
operation, must be set up in this register before triggering the write. When
the channel FIFO free space reaches or exceeds the limit specified by
XFER[3:0], the partial packet processor will make a request for data to the
TMAC672 to retrieve the XFER[3:0] + 1 blocks of data. FIFO free space and
transfer size are measured in the number of 16-byte blocks. XFER[3:0]
reflects the value written until the completion of a subsequent indirect channel
read operation.
To prevent lockup, the channel transfer size (XFER[3:0]) can be configured to
be less than or equal to the start transmission level set by LEVEL[3:0] and
TRANS. Alternatively, the channel transfer size can be set, such that, the
total number of blocks in the logical channel FIFO minus the start
transmission level is an integer multiple of the channel transfer size.
The case of a single block transfer size is a special. When BURSTEN is set
high and XFER[3:0] = 'b0000, the transfer size is variable. The THDL672 will
request the TMAC672 to transfer as much data as there is free space in the
FIFO, up to a maximum set by BURST[3:0].
FLAG[2:0]:
The flag insertion control (FLAG[2:0]) configures the minimum number of
flags or bytes of idle bits the HDLC processor inserts between HDLC packets.
The value of FLAG[2:0] to be written to the channel provision RAM, in an
indirect channel write operation, must be set up in this register before
triggering the write. The minimum number of flags or bytes of idle (8 bits of
1's) inserted between HDLC packets is shown in the table below. FLAG[2:0]
reflects the value written until the completion of a subsequent indirect channel
read operation.
Table 25 – FLAG[2:0] Settings
FLAG[2:0] Minimum Number of Flag/Idle Bytes
000
001
010
011
100
1 flag / 0 Idle byte
2 flags / 0 idle byte
4 flags / 2 idle bytes
8 flags / 6 idle bytes
16 flags / 14 idle bytes
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
219
PMC [ PMC-SIERRA, INC ]
