RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
implemented. However, when all four byte enables are negated, no access is
made to this register.
CHAN[9:0]:
The indirect data bits (CHAN[9:0]) report the channel number read from the
TMAC672 internal memory after an indirect read operation has completed.
Channel number to be written to the TMAC672 internal memory in an indirect
write operation must be set up in this register before triggering the write.
CHAN[9:0] reflects the value written until the completion of a subsequent
indirect read operation.
PROV:
The indirect provision enable bit (PROV) reports the channel provision enable
flag read from the TMAC672 internal memory after an indirect read operation
has completed. The provision enable flag to be written to the TMAC672
internal memory, in an indirect write operation, must be set up in this register
before triggering the write. When PROV is set high, the channel as indicated
by CHAN[9:0] is provisioned. When PROV is set low, the channel indicated
by CHAN[9:0] is unprovisioned. PROV reflects the value written until the
completion of a subsequent indirect read operation.
RWB:
The Read/Write Bar (RWB) bit selects between a provisioning/unprovisioning
operation (write) or a query operation (read). Writing a logic 0 to RWB
triggers the provisioning or unprovisioning of a channel as specified by
CHAN[9:0] and PROV. Writing a logic 1 to RWB triggers a query of the
channel specified by CHAN[9:0].
BUSY:
The indirect access status bit (BUSY) reports the progress of an indirect
access. BUSY is set high when this register is written to trigger an indirect
access, and will stay high until the access is complete. At which point, BUSY
will be set low. This register should be polled to determine when data from an
indirect read operation is available or to determine when a new indirect write
operation may commence.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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