RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
Register 0x300 : TMAC Control
Bit
Type
Function
Default
Bit 31
to
Unused
XXXXXXH
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FQFLUSH
TDQ_FRN[1]
TDQ_FRN[0]
TDQ_RDYN[2]
TDQ_RDYN[1]
TDQ_RDYN[0]
CACHE
0
0
0
0
0
0
1
0
ENABLE
This register provides control of the TMAC672 block.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
ENABLE:
The transmit DMA controller enable bit (ENABLE) enables the TMAC672 to
accept TDRs from the TDR Ready Queue and reads packet data from host
memory. When ENABLE is set high, the TMAC672 is enabled. When
ENABLE is set low, the TDR Ready Queue is ignored. Once all linked lists of
TDs built up by the TMAC672 have been exhausted, no more data will be
transmitted on the TD[31:0] links.
CACHE:
The transmit descriptor reference cache enable bit (CACHE) controls the
frequency at which TDRs are written to the TDR Free Queue. When CACHE
is set high, freed TDRs are cached and then written up to six at a time.
When CACHE is set low, freed TDRs are written one at a time.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
184
PMC [ PMC-SIERRA, INC ]
