欢迎访问ic37.com |
会员登录 免费注册
发布采购

PM7380-PI 参数 Datasheet PDF下载

PM7380-PI图片预览
型号: PM7380-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 帧引擎和数据链路管理32P672 [FRAME ENGINE AND DATA LINK MANAGER 32P672]
分类和应用:
文件页数/大小: 332 页 / 2479 K
品牌: PMC [ PMC-SIERRA, INC ]
 浏览型号PM7380-PI的Datasheet PDF文件第170页浏览型号PM7380-PI的Datasheet PDF文件第171页浏览型号PM7380-PI的Datasheet PDF文件第172页浏览型号PM7380-PI的Datasheet PDF文件第173页浏览型号PM7380-PI的Datasheet PDF文件第175页浏览型号PM7380-PI的Datasheet PDF文件第176页浏览型号PM7380-PI的Datasheet PDF文件第177页浏览型号PM7380-PI的Datasheet PDF文件第178页  
RELEASED  
PM7380 FREEDM-32P672  
DATA SHEET  
PMC-1990262  
ISSUE 5  
FRAME ENGINE AND DATA LINK MANAGER 32P672  
2. If consecutive write accesses to this register are performed, they must be  
spaced at least 4 SYSCLK periods apart.  
RPDRLFQW[15:0]:  
The receive packet descriptor reference (RPDR) large buffer free queue write  
bits (RPDRLFQW[15:0]) define bits 17 to 2 of the Receive Packet Descriptor  
Reference Large Buffer Free Queue write pointer. This register is initialised  
by the host. The physical write address in the RPDRLF queue is the sum of  
RPDRLFQW[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC  
Receive Queue Base register.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
163  
 复制成功!