RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
TLGA[4]:
The transmit link group #4 active bit (TLGA[4]) monitors for low to high
transitions on the TCLK[19:16] inputs. TLGA[4] is set high when rising edges
have been observed on all four TCLK[19:16] inputs, and is set low when this
register is read.
TLGA[5]:
The transmit link group #5 active bit (TLGA[5]) monitors for low to high
transitions on the TCLK[23:20] inputs. TLGA[5] is set high when rising edges
have been observed on all four TCLK[23:20] inputs, and is set low when this
register is read.
TLGA[6]:
The transmit link group #6 active bit (TLGA[6]) monitors for low to high
transitions on the TCLK[27:24] inputs. TLGA[6] is set high when rising edges
have been observed on all four TCLK[27:24] inputs, and is set low when this
register is read.
TLGA[7]:
The transmit link group #7 active bit (TLGA[7]) monitors for low to high
transitions on the TCLK[31:28] & TMV8DC inputs. TLGA[7] is set high when
either:
1. Rising edges have been observed on all four TCLK[31:28] inputs, or
2. A rising edge has been observed on the TMV8DC input.
TLGA[7] is set low when this register is read.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
106
PMC [ PMC-SIERRA, INC ]
