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PM7380-PI 参数 Datasheet PDF下载

PM7380-PI图片预览
型号: PM7380-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 帧引擎和数据链路管理32P672 [FRAME ENGINE AND DATA LINK MANAGER 32P672]
分类和应用:
文件页数/大小: 332 页 / 2479 K
品牌: PMC [ PMC-SIERRA, INC ]
 浏览型号PM7380-PI的Datasheet PDF文件第112页浏览型号PM7380-PI的Datasheet PDF文件第113页浏览型号PM7380-PI的Datasheet PDF文件第114页浏览型号PM7380-PI的Datasheet PDF文件第115页浏览型号PM7380-PI的Datasheet PDF文件第117页浏览型号PM7380-PI的Datasheet PDF文件第118页浏览型号PM7380-PI的Datasheet PDF文件第119页浏览型号PM7380-PI的Datasheet PDF文件第120页  
RELEASED  
PM7380 FREEDM-32P672  
DATA SHEET  
PMC-1990262  
ISSUE 5  
FRAME ENGINE AND DATA LINK MANAGER 32P672  
RLGA[7]:  
The receive link group #7 active bit (RLGA[7]) monitors for transitions on the  
RD[31:28] and RCLK[31:28]/RMVCK[3]/RMV8DC inputs. RLGA[7] is set high  
when either:  
1. Each of RD[31:28] has been sampled low and sampled high by rising  
edges of the corresponding RCLK[31:28] inputs, or  
2. Each of RD[31:28] has been sampled low and sampled high by rising  
edges of the RMVCK[3] input, or  
3. RD[28] has been sampled low and sampled high by rising edges of the  
RMV8DC input.  
RLGA[7] is set low when this register is read.  
TLGA[0]:  
The transmit link group #0 active bit (TLGA[0]) monitors for low to high  
transitions on the TCLK[3:0] & TMVCK[0] inputs. TLGA[0] is set high when  
either:  
1. Rising edges have been observed on all four TCLK[3:0] inputs, or  
2. A rising edge has been observed on the TMVCK[0] input.  
TLGA[0] is set low when this register is read.  
TLGA[1]:  
The transmit link group #1 active bit (TLGA[1]) monitors for low to high  
transitions on the TCLK[7:4] & TMVCK[1] inputs. TLGA[1] is set high when  
either:  
1. Rising edges have been observed on all four TCLK[7:4] inputs, or  
2. A rising edge has been observed on the TMVCK[1] input.  
TLGA[1] is set low when this register is read.  
TLGA[2]:  
The transmit link group #2 active bit (TLGA[2]) monitors for low to high  
transitions on the TCLK[11:8] & TMVCK[2] inputs. TLGA[2] is set high when  
either:  
1. Rising edges have been observed on all four TCLK[11:8] inputs, or  
2. A rising edge has been observed on the TMVCK[2] input.  
TLGA[2] is set low when this register is read.  
TLGA[3]:  
The transmit link group #3 active bit (TLGA[3]) monitors for low to high  
transitions on the TCLK[15:12] & TMVCK[3] inputs. TLGA[3] is set high when  
either:  
1. Rising edges have been observed on all four TCLK[15:12] inputs, or  
2. A rising edge has been observed on the TMVCK[3] input.  
TLGA[3] is set low when this register is read.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
105  
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