RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
FIGURE 46 – BERT INPUT TIMING ...............................................................311
FIGURE 47 – TRANSMIT DATA & FRAME PULSE TIMING (2.048 MBPS
H-MVIP MODE).....................................................................................313
FIGURE 48 – TRANSMIT DATA & FRAME PULSE TIMING (8.192 MBPS
H-MVIP MODE).....................................................................................314
FIGURE 49 – TRANSMIT DATA TIMING (NON H-MVIP MODE)....................314
FIGURE 50 – BERT OUTPUT TIMING ...........................................................315
FIGURE 51 – PCI INTERFACE TIMING .........................................................316
FIGURE 52 – JTAG PORT INTERFACE TIMING............................................317
FIGURE 53 – 329 PIN PLASTIC BALL GRID ARRAY (PBGA) .......................319
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
viii
PMC [ PMC-SIERRA, INC ]
