RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
supports the validation of both CRC-CCITT and CRC-32 frame check
sequences.
Sꢀ For each channel, the receiver checks for packet abort sequences, octet
aligned packet length and for minimum and maximum packet length. The
receiver supports filtering of packets that are larger than a user specified
maximum value.
Sꢀ Alternatively, for each channel, the receiver supports a transparent mode
where each octet is transferred transparently to host memory. For
channelised links, the octets are aligned with the receive time-slots.
Sꢀ For each channel, time-slots are selectable to be in 56 kbits/s format or 64
kbits/s clear channel format.
Sꢀ For each channel, the HDLC transmitter supports programmable flag
sequence generation, bit stuffing and frame check sequence generation. The
transmitter supports the generation of both CRC-CCITT and CRC-32 frame
check sequences. The transmitter also aborts packets under the direction of
the host or automatically when the channel underflows.
Sꢀ Supports two levels of non-preemptive packet priority on each transmit
channel. Low priority packets will not begin transmission until all high priority
packets are transmitted.
Sꢀ Alternatively, for each channel, the transmitter supports a transparent mode
where each octet is inserted transparently from host memory. For
channelised links, the octets are aligned with the transmit time-slots.
Sꢀ Provides 32 Kbytes of on-chip memory for partial packet buffering in both the
transmit and receive directions. This memory may be configured to support a
variety of different channel configurations from a single channel with 32
Kbytes of buffering to 672 channels, each with a minimum of 48 bytes of
buffering.
Sꢀ Supports PCI burst sizes of up to 256 bytes for transfers of packet data.
Sꢀ Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board
test purposes.
Sꢀ Supports 3.3 Volt PCI signaling environments.
Sꢀ Supports 5 Volt tolerant I/O (except PCI).
Sꢀ Low power 2.5 Volt 0.25 ꢁm CMOS technology.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
2
PMC [ PMC-SIERRA, INC ]
