RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
Pin Name Type
Pin
Function
No.
TRDB
Input
Input
I/O
A18
The test mode read enable signal (TRDB) is set
low during FREEDM-32P672 register read
accesses during production test (PMCTEST set
high). The FREEDM-32P672 drives the test data
bus (TDAT[15:0]) with the contents of the
addressed register while TRDB is low. TRDB
replaces RD[22] when PMCTEST is set high.
TWRB
A17
The test mode write enable signal (TWRB) is set
low during FREEDM-32P672 register write
accesses during production test (PMCTEST set
high). The contents of the test data bus
(TDAT[15:0]) are clocked into the addressed
register on the rising edge of TWRB. TWRB
replaces RD[23] when PMCTEST is set high.
TDAT[0]
TDAT[1]
TDAT[2]
TDAT[3]
TDAT[4]
TDAT[5]
TDAT[6]
TDAT[7]
TDAT[8]
TDAT[9]
TDAT[10]
TDAT[11]
TDAT[12]
TDAT[13]
TDAT[14]
TDAT[15]
AC1 The bi-directional test mode data bus
4
(TDAT[15:0]) carries data read from or written to
AA14 FREEDM-32P672 registers during production
AC1 test. TDAT[15:0] replace TD[31:16] when
3
PMCTEST is set high.
AB13
AA12
AB11
Y11
AB10
Y9
AA8
AC8
AB7
AC7
AC6
AC5
AB4
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
34
PMC [ PMC-SIERRA, INC ]
