RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
Table 2 – PCI Host Interface Signals (52)
Pin Name Type
Pin
No.
Function
PCICLK
Input
Output
I/O
G3
The PCI clock signal (PCICLK) provides timing
for PCI bus accesses. PCICLK is a nominally
50% duty cycle, 25 to 66 MHz clock.
The PCI clock output signal (PCICLKO) is a
buffered version of the PCICLK. PCICLKO may
be used to derive the SYSCLK input.
The PCI bus command and byte enable bus
(C/BEB[3:0]) contains the bus command or the
byte valid indications. During the first clock
cycle of a transaction, C/BEB[3:0] contains the
bus command code. For subsequent clock
cycles, C/BEB[3:0] identifies which bytes on the
AD[31:0] bus carry valid data. C/BEB[3] is
associated with byte 3 (AD[31:24]) while
C/BEB[0] is associated with byte 0 (AD[7:0]).
When C/BEB[n] is set high, the associated byte
is invalid. When C/BEB[n] is set low, the
associated byte is valid.
PCICLKO
G4
C/BEB[0]
C/BEB[1]
C/BEB[2]
C/BEB[3]
Y2
U3
P3
L4
When the FREEDM-32P672 is the initiator,
C/BEB[3:0] is an output bus.
When the FREEDM-32P672 is the target,
C/BEB[3:0] is an input bus.
When the FREEDM-32P672 is not involved in
the current transaction, C/BEB[3:0] is tristated.
As an output bus, C/BEB[3:0] is updated on the
rising edge of PCICLK. As an input bus,
C/BEB[3:0] is sampled on the rising edge of
PCICLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
23
PMC [ PMC-SIERRA, INC ]
