欢迎访问ic37.com |
会员登录 免费注册
发布采购

PM7380 参数 Datasheet PDF下载

PM7380图片预览
型号: PM7380
PDF下载: 下载PDF文件 查看货源
内容描述: 帧引擎和数据链路管理32P672 [FRAME ENGINE AND DATA LINK MANAGER 32P672]
分类和应用:
文件页数/大小: 332 页 / 2479 K
品牌: PMC [ PMC-SIERRA, INC ]
 浏览型号PM7380的Datasheet PDF文件第147页浏览型号PM7380的Datasheet PDF文件第148页浏览型号PM7380的Datasheet PDF文件第149页浏览型号PM7380的Datasheet PDF文件第150页浏览型号PM7380的Datasheet PDF文件第152页浏览型号PM7380的Datasheet PDF文件第153页浏览型号PM7380的Datasheet PDF文件第154页浏览型号PM7380的Datasheet PDF文件第155页  
RELEASED  
PM7380 FREEDM-32P672  
DATA SHEET  
PMC-1990262  
ISSUE 5  
FRAME ENGINE AND DATA LINK MANAGER 32P672  
CRC[1]  
CRC[0]  
Operation  
Reserved  
1
1
INVERT:  
The HDLC data inversion bit (INVERT) configures the HDLC processor to  
logically invert the incoming HDLC stream from the RCAS672 before  
processing it. The value of INVERT to be written to the channel provision  
RAM, in an indirect channel write operation, must be set up in this register  
before triggering the write. When INVERT is set to one, the HDLC stream is  
logically inverted before processing. When INVERT is set to zero, the HDLC  
stream is not inverted before processing. INVERT reflects the value written  
until the completion of a subsequent indirect channel read operation.  
PRIORITY:  
The channel FIFO priority bit (PRIORITY) informs the partial packet  
processor that the channel has precedence over other channels when being  
serviced by the RMAC672 block for transfer to the PCI host. The value of  
PRIORITY to be written to the channel provision RAM, in an indirect channel  
write operation, must be set up in this register before triggering the write.  
Channel FIFOs with PRIORITY set to one are serviced by the RMAC672  
before channel FIFOs with PRIORITY set to zero. Channels with an HDLC  
data rate to FIFO size ratio that is significantly higher than other channels  
should have PRIORITY set to one. PRIORITY reflects the value written until  
the completion of a subsequent indirect channel read operation.  
7BIT:  
The 7BIT enable bit (7BIT) configures the HDLC processor to ignore the least  
significant bit of each octet in the corresponding link RD[n]. The value of  
7BIT to be written to the channel provision RAM, in an indirect channel write  
operation, must be set up in this register before triggering the write. When  
7BIT is set high, the least significant bit (last bit of each octet received), is  
ignored. When 7BIT is set low, the entire receive data stream is processed.  
7BIT reflects the value written until the completion of a subsequent indirect  
channel read operation.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
140  
 复制成功!