RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
Register 0x020 : FREEDM-32P672 Master BERT Control
Bit
Type
Function
Default
Bit 31
to
Unused
XXXXH
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
R/W
TBEN
Unused
Unused
TBSEL[4]
TBSEL[3]
TBSEL[2]
TBSEL[1]
TBSEL[0]
RBEN
0
X
X
0
0
0
0
0
0
X
X
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Unused
Unused
Bit 4
Bit 3
Bit 2
Bit 1
R/W
R/W
R/W
R/W
R/W
RBSEL[4]
RBSEL[3]
RBSEL[2]
RBSEL[1]
RBSEL[0]
Bit 0
This register controls the bit error rate testing of the receive and transmit links.
Bit error rate testing is not supported for links configured for H-MVIP traffic.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
112
PMC [ PMC-SIERRA, INC ]
