RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
Pin Name
Type
Pin No.
Function
-PI
-BI
PAR
I/O
M19
N1
The parity signal (PAR) indicates the parity of the
AD[31:0] and C/BEB[3:0] buses. Even parity is
calculated over all 36 signals in the buses regardless
of whether any or all the bytes on the AD[31:0] are
valid. PAR always reports the parity of the previous
PCICLK cycle. Parity errors detected by the
FREEDM-8 are indicated on output PERRB and in
the FREEDM-8 Interrupt Status register.
When the FREEDM-8 is the initiator, PAR is an output
for writes and an input for reads.
When the FREEDM-8 is the target, PAR is an input
for writes and an output for reads.
When the FREEDM-8 is not involved in the current
transaction, PAR is tri-stated.
As an output signal, PAR is updated on the rising
edge of PCICLK. As an input signal, PAR is sampled
on the rising edge of PCICLK.
FRAMEB
I/O
K17
K4
The active low cycle frame signal (FRAMEB)
identifies a transaction cycle. When FRAMEB
transitions low, the start of a bus transaction is
indicated. FRAMEB remains low to define the
duration of the cycle. When FRAMEB transitions
high, the last data phase of the current transaction is
indicated.
When the FREEDM-8 is the initiator, FRAMEB is an
output.
When the FREEDM-8 is the target, FRAMEB is an
input.
When the FREEDM-8 is not involved in the current
transaction, FRAMEB is tri-stated.
As an output signal, FRAMEB is updated on the rising
edge of PCICLK. As an input signal, FRAMEB is
sampled on the rising edge of PCICLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
17
PMC [ PMC-SIERRA, INC ]
