RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
controller interprets the TMS input and generates control signals to load the instruction and data
registers. The instruction register with instruction decode block is used to select the test to be
executed and/or the register to be accessed. The bypass register offers a single bit delay from
primary input, TDI to primary output , TDO. The device identification register contains the device
identification code.
The boundary scan register allows testing of board inter-connectivity. The boundary scan register
consists of a shift register placed in series with device inputs and outputs. Using the boundary
scan register, all digital inputs can be sampled and shifted out on primary output TDO. In addition,
patterns can be shifted in on primary input, TDI and forced onto all digital outputs.
TAP Controller
The TAP controller is a synchronous finite state machine clocked by the rising edge of primary
input, TCK. All state transitions are controlled using primary input, TMS. The finite state machine
is described below.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
243
PMC [ PMC-SIERRA, INC ]
