RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
All 8 framers in the TOCTL should be programmed to operate in “Clock Master: NxDS0” mode in
both the ingress and egress direction.
13.3 JTAG Support
The FREEDM-8 supports the IEEE Boundary Scan Specification as described in the IEEE 1149.1
standards. The Test Access Port (TAP) consists of the five standard pins, TRSTB, TCK, TMS,
TDI and TDO used to control the TAP controller and the boundary scan registers. The TRSTB
input is the active low reset signal used to reset the TAP controller. TCK is the test clock used to
sample data on input, TDI and to output data on output, TDO. The TMS input is used to direct the
TAP controller through its states. The basic boundary scan architecture is shown below.
Figure 20 – Boundary Scan Architecture
Boundary Scan
TDI
Register
Device Identification
Register
Bypass
Register
Instruction
Mux
Register
DFF
TDO
and
Decode
Control
TMS
Test
Access
Port
Select
Controller
Tri-state Enable
TRSTB
TCK
The boundary scan architecture consists of a TAP controller, an instruction register with instruction
decode, a bypass register, a device identification register and a boundary scan register. The TAP
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
242
PMC [ PMC-SIERRA, INC ]
