RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
can be reset, but not set. A bit is reset whenever the register is written, and the data in the
corresponding bit location is a 1.
IOCNTRL:
When IOCNTRL is set to zero, the GPIC will not respond to PCI bus I/O accesses.
MCNTRL:
When MCNTRL is set to one, the GPIC will respond to PCI bus memory accesses. Clearing
MCNTRL disables memory accesses.
MSTREN:
When MSTREN is set to one, the GPIC can act as a Master. Clearing MSTREN disables the
GPIC from becoming a Master.
SPCEN:
The GPIC does not decode PCI special cycles. The SPCEN bit is forced low.
MWAI:
The GPIC does not generate memory-write-and-invalidate commands. The MWAI bit is forced
low.
VGASNP:
The GPIC is not a VGA device. The VGASNP bit is forced low.
PERREN:
When the PERREN bit is set to one, the GPIC can report parity errors. Clearing the PERREN
bit causes the GPIC to ignore parity errors.
ADSTP:
The GPIC does not perform address and data stepping. The ADSTP bit is forced low.
SERREN:
When the SERREN bit is set high, the GPIC can drive the SERRB line. Clearing the SERREN
bit disables the SERRB line. SERREN and PERREN must be set to report an address parity
error.
FBTBEN:
As a master, the GPIC does not generate fast back-to-back cycles to different devices. This
bit is forced low.
The upper 16-bits make up the PCI Status field. The status field tracks the status of PCI bus
related events. Reads to this register behave normally. Writes are slightly different in that bits can
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
219
PMC [ PMC-SIERRA, INC ]
