RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
Register 0x04 : Command/Status
Bit
Type
Function
Default
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Bit 23
R/W
R/W
R/W
R/W
R/W
R
PERR
SERR
0
0
MABT
0
RTABT
TABT
0
0
DVSLT[1]
DVSLT[0]
DPR
0
R
1
R/W
R
0
FBTBE
Reserved
1
Bit 22
to
Bit 16
R
00H
Bit 15
to
Bit 10
R
Reserved
00H
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R/W
R
FBTBEN
SERREN
ADSTP
0
0
0
0
0
0
0
0
0
0
R/W
R
PERREN
VGASNP
MWAI
R
R
SPCEN
R/W
R/W
R
MSTREN
MCNTRL
IOCNTRL
The lower 16 bits of this register make up the Command register which provides basic control
over the GPIC's ability to respond to PCI accesses. When a 0 is written to all bits in the command
register, the GPIC is logically disconnected from the PCI bus for all accesses except configuration
accesses. The upper 16-bits is used to record status information for PCI bus related events.
Reads to the status portion of this register behave normally. Writes are slightly different in that bits
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
218
PMC [ PMC-SIERRA, INC ]
