RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
unchannelised and the E1 register bit is ignored. TCLK[n] is gapped during non-data bytes.
The choice between treating all data bits as a contiguous stream with arbitrary byte alignment
or byte aligned to gaps in TCLK[n] is controlled by the BSYNC bit.
E1:
The E1 frame structure select bit (E1) configures the corresponding link for channelised E1
operation when CEN is set high. TCLK[n] is held quiescent during the FAS and NFAS framing
bytes. The most significant bit of time-slot 1 is placed on TD[n] on the last falling edge of
TCLK[n] ahead of the extended quiescent period. Link data is present at time-slots 1 to 31.
When E1 is set low and CEN is set high, the corresponding link is configured for channelised
T1 operation. TCLK[n] is held quiescent during the framing bit. The m.s.b. of time-slot 1 is
placed on TD[n] on the last falling edge of TCLK[n] ahead of the extended quiescent period.
Link data is present at time-slots 1 to 24. E1 is ignored when CEN is set low.
BSYNC:
The byte synchronisation enable bit (BSYNC) controls the interpretation of gaps in TCLK[n]
when the corresponding link is in unchannelised mode (CEN set low). When BSYNC is set
high, the data bit on TD[n] clocked in by a downstream device on the first rising edge of
TCLK[n] after an extended quiescent period is considered to be the most significant bit of a
data byte. When BSYNC is set low, gaps in TCLK[n] carry no special significance. BSYNC is
ignored when CEN is set high.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
201
PMC [ PMC-SIERRA, INC ]
