RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
Register 0x410 : TCAS Channel Disable
Bit
Type
Function
Default
Bit 31 to
Bit 16
Unused
XXXXH
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
R/W
CHDIS
Unused
0
X
X
X
X
X
X
X
X
0
Unused
Unused
Unused
Unused
Unused
Bit 8
Unused
Bit 7
Unused
Bit 6
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DCHAN[6]
DCHAN[5]
DCHAN[4]
DCHAN[3]
DCHAN[2]
DCHAN[1]
DCHAN[0]
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
This register controls the disabling of one specific channel to allow orderly provisioning of
timeslots.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register.
Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all
four byte enables are negated, no access is made to this register.
DCHAN[6:0]:
The disable channel number bits (DCHAN[6:0]) selects the channel to be disabled. When
CHDIS is set high, the channel specified by DCHAN[6:0] is disabled. Data in timeslots
associated with the specified channel is set to FDATA[7:0] in the Idle Time-slot Fill Data
register. When CHDIS is set low, the channel specified by DCHAN[6:0] operates normally.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
196
PMC [ PMC-SIERRA, INC ]
