RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
Register 0x40C : TCAS Idle Time-slot Fill Data
Bit
Type
Function
Default
Bit 31 to
Bit 16
Unused
XXXXH
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Unused
Unused
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
Unused
Unused
Unused
Unused
Unused
Bit 8
Unused
Bit 7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FDATA[7]
FDATA[6]
FDATA[5]
FDATA[4]
FDATA[3]
FDATA[2]
FDATA[1]
FDATA[0]
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
This register contains the data to be written to disabled time-slots of a channelised link.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register.
Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all
four byte enables are negated, no access is made to this register.
FDATA[7:0]:
The fill data bits (FDATA[7:0]) are transmitted during disabled (PROV set low) time-slots of
channelised links.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
195
PMC [ PMC-SIERRA, INC ]
