RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
Register 0x3B0 : THDL Configuration
Bit
Type
Function
Default
Bit 31 to
Bit 16
Unused
XXXXH
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Unused
Unused
Unused
Unused
Unused
Unused
BIT8
X
X
X
X
X
X
0
R/W
R/W
R/W
Bit 8
TSTD
0
Bit 7
BURSTEN
Unused
Unused
Unused
Unused
BURST[2]
BURST[1]
BURST[0]
0
Bit 6
X
X
X
X
0
Bit 5
Bit 4
Bit 3
Bit 2
R/W
R/W
R/W
Bit 1
0
Bit 0
0
This register configures all provisioned channels.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register.
Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all
four byte enables are negated, no access is made to this register.
BURST[2:0]:
The DMA burst length bits (BURST[2:0]) configure the maximum amount of transmit data that
can be requested in a single DMA transaction for channels whose channel transfer size is set
to one block (XFER[2:0] = 'b000). BURST[2:0] has no effect when BURSTEN is set low, nor
on channels configured with other transfer sizes. BURST[2:0] defines the maximum number
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
187
PMC [ PMC-SIERRA, INC ]
