RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
Register 0x32C : TMAC Descriptor Reference Ready Queue Write
Bit
Type
Function
Default
Bit 31 to
Bit 16
Unused
XXXXH
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TDRRQW[15]
TDRRQW[14]
TDRRQW[13]
TDRRQW[12]
TDRRQW[11]
TDRRQW[10]
TDRRQW[9]
TDRRQW[8]
TDRRQW[7]
TDRRQW[6]
TDRRQW[5]
TDRRQW[4]
TDRRQW[3]
TDRRQW[2]
TDRRQW[1]
TDRRQW[0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
This register provides the Transmit Descriptor Reference Ready Queue write address.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register.
Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all
four byte enables are negated, no access is made to this register.
TDRRQW[15:0]:
The transmit packet descriptor reference (TPDR) ready queue write bits (TDRRQW[15:0])
define bits 17 to 2 of the Transmit Packet Descriptor Reference Ready Queue write pointer.
This register is initialised by the host. The physical write address in the TDRF queue is the
sum of TDRRQW[15:0] left shifted by 2 bits with the TQB[31:0] bits in the TMAC Transmit
Queue Base register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
169