RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
Register 0x324 : TMAC Descriptor Reference Free Queue End
Bit
Type
Function
Default
Bit 31 to
Bit 16
Unused
XXXXH
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TDRFQE[15]
TDRFQE[14]
TDRFQE[13]
TDRFQE[12]
TDRFQE[11]
TDRFQE[10]
TDRFQE[9]
TDRFQE[8]
TDRFQE[7]
TDRFQE[6]
TDRFQE[5]
TDRFQE[4]
TDRFQE[3]
TDRFQE[2]
TDRFQE[1]
TDRFQE[0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
This register provides the Transmit Descriptor Reference Free Queue end address.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register.
Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all
four byte enables are negated, no access is made to this register.
TDRFQE[15:0]:
The transmit packet descriptor reference (TDR) free queue end bits (TDRFQE[15:0]) define
bits 17 to 2 of the Transmit Packet Descriptor Reference Free Queue end address. This
register is initialised by the host. The physical end address of the TDRF queue is the sum of
TDRFQE[15:0] left shifted by 2 bits with the TQB[31:0] bits in the TMAC Transmit Queue Base
register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
167