RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
Register 0x314 : TMAC Queue Base MSW
Bit
Type
Function
Default
Bit 31 to
Bit 16
Unused
XXXXH
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TQB[31]
TQB[30]
TQB[29]
TQB[28]
TQB[27]
TQB[26]
TQB[25]
TQB[24]
TQB[23]
TQB[22]
TQB[21]
TQB[20]
TQB[19]
TQB[18]
TQB[17]
TQB[16]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
This register provides the more significant word of the Transmit Queue Base address. The
contents of the companion TMAC Transmit Descriptor Table Base LSW register is held in a
holding register until a write access to this register, at which point, the base address of the
transmit queue is updated.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register.
Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all
four byte enables are negated, no access is made to this register.
TQB[31:0]:
The transmit queue base bits (TQB[31:0]) provides the base address of the Transmit
Descriptor Reference Free and Transmit Descriptor Reference Ready queue in PCI host
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
162
PMC [ PMC-SIERRA, INC ]
