RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
Register 0x300 : TMAC Control
Bit
Type
Function
Default
Bit 31 to
Bit 16
Unused
XXXXH
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Unused
Unused
X
X
X
X
X
X
X
X
X
0
Unused
Unused
Unused
Unused
Unused
Bit 8
Unused
Bit 7
Unused
Bit 6
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TDQ_FRN[1]
TDQ_FRN[0]
TDQ_RDYN[2]
TDQ_RDYN[1]
TDQ_RDYN[0]
CACHE
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
1
Bit 0
ENABLE
0
This register provides control of the TMAC block.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register.
Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all
four byte enables are negated, no access is made to this register.
ENABLE:
The transmit DMA controller enable bit (ENABLE) enables the TMAC to accept TDRs from
the TDR Ready Queue and reads packet data from host memory. When ENABLE is set high,
the TMAC is enabled. When ENABLE is set low, the TDR Ready Queue is ignored. Once all
linked lists of TDs built up by the TMAC have been exhausted, no more data will be
transmitted on the TD[31:0] links.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
154
PMC [ PMC-SIERRA, INC ]
