RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
Register 0x2C4 : RMAC Packet Descriptor Reference Ready Queue End
Bit
Type
Function
Default
Bit 31 to
Bit 16
Unused
XXXXH
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RPDRRQE[15]
RPDRRQE[14]
RPDRRQE[13]
RPDRRQE[12]
RPDRRQE[11]
RPDRRQE[10]
RPDRRQE[9]
RPDRRQE[8]
RPDRRQE[7]
RPDRRQE[6]
RPDRRQE[5]
RPDRRQE[4]
RPDRRQE[3]
RPDRRQE[2]
RPDRRQE[1]
RPDRRQE[0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
This register provides the Packet Descriptor Reference Ready Queue end address.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register.
Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all
four byte enables are negated, no access is made to this register.
RPDRRQE[15:0]:
The receive packet descriptor reference (RPDR) ready queue end bits (RPDRRQE[15:0])
define bits 17 to 2 of the Receive Packet Descriptor Reference Ready Queue end address.
This register is initialised by the host. The physical end address in the RPDRR queue is the
sum of RPDRRQE[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive
Queue Base register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
153