RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
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FEATURES
Sꢀ Single-chip Peripheral Component Interconnect (PCI) Bus multi-channel HDLC controller.
Sꢀ Supports up to 128 bi-directional HDLC channels assigned to a maximum of 8 channelised T1
or E1 links. The number of time-slots assigned to an HDLC channel is programmable from 1
to 24 (for T1) and from 1 to 31 (for E1).
Sꢀ Supports up to 8 bi-directional HDLC channels each assigned to an unchannelised arbitrary
rate link; subject to a maximum aggregate link clock rate of 64 MHz in each direction.
Channels assigned to links 0 to 2 can have a clock rate of up 52 MHz when SYSCLK is at 33
MHz. Channels assigned to links 3 to 7 can have a clock rate of up to 10 MHz.
Sꢀ Supports up to two bi-directional HDLC Channels each assigned to an unchannelised arbitrary
rate link of up to 52 MHz when SYSCLK is at 33 MHz.
Sꢀ Supports a mix of up to 8 channelised and unchannelised links; subject to the constraint of a
maximum of 128 channels and a maximum aggregate link clock rate of 64 MHz in each
direction.
Sꢀ For each channel, the HDLC receiver performs flag sequence detection, bit de-stuffing, and
frame check sequence validation. The receiver supports the validation of both CRC-CCITT
and CRC-32 frame check sequences. The receiver also checks for packet abort sequences,
octet aligned packet length and for minimum and maximum packet length.
Sꢀ Alternatively, for each channel, the receiver supports a transparent mode where each octet is
transferred transparently to host memory. For channelised links, the octets are aligned with
the receive time-slots.
Sꢀ For each channel, time-slots are selectable to be in 56 kbits/s format or 64 kbits/s clear
channel format.
Sꢀ For each channel, the HDLC transmitter performs flag sequence generation, bit stuffing, and,
optionally, frame check sequence generation. The transmitter supports the generation of
both CRC-CCITT and CRC-32 frame check sequences. The transmitter also aborts packets
under the direction of the host or automatically when the channel underflows.
Sꢀ Supports two levels of non-preemptive packet priority on each transmit channel. Low priority
packets will not begin transmission until all high priority packets are transmitted.
Sꢀ Alternatively, for each channel, the transmitter supports a transparent mode where each octet
is inserted transparently from host memory. For channelised links, the octets are aligned with
the transmit time-slots.
Sꢀ Directly supports a 32-bit, 33 MHz PCI 2.1 interface for configuration, monitoring and transfer
of packet data, with an on-chip DMA controller with scatter/gather capabilities.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC [ PMC-SIERRA, INC ]
