RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
LIST OF FIGURES
FIGURE 1 – HDLC FRAME ......................................................................................................... 33
FIGURE 2 – CRC GENERATOR ................................................................................................. 33
FIGURE 3 – PARTIAL PACKET BUFFER STRUCTURE ............................................................ 37
FIGURE 4 – RECEIVE PACKET DESCRIPTOR ......................................................................... 39
FIGURE 5 – RECEIVE PACKET DESCRIPTOR TABLE............................................................. 42
FIGURE 6 – RPDRF AND RPDRR QUEUES.............................................................................. 44
FIGURE 7 – RPDRR QUEUE OPERATION................................................................................ 46
FIGURE 8 – RECEIVE CHANNEL DESCRIPTOR REFERENCE TABLE................................... 47
FIGURE 9 – GPIC ADDRESS MAP............................................................................................. 53
FIGURE 10 – TRANSMIT DESCRIPTOR.................................................................................... 55
FIGURE 11 – TRANSMIT DESCRIPTOR TABLE........................................................................ 58
FIGURE 12 – TDRR AND TDRF QUEUES ................................................................................. 60
FIGURE 13 – TRANSMIT CHANNEL DESCRIPTOR REFERENCE TABLE .............................. 62
FIGURE 14 – TD LINKING .......................................................................................................... 65
FIGURE 15 – PARTIAL PACKET BUFFER STRUCTURE .......................................................... 68
FIGURE 16 – INPUT OBSERVATION CELL (IN_CELL) ........................................................... 238
FIGURE 17 – OUTPUT CELL (OUT_CELL).............................................................................. 239
FIGURE 18 – BI-DIRECTIONAL CELL (IO_CELL).................................................................... 239
FIGURE 19 – LAYOUT OF OUTPUT ENABLE AND BI-DIRECTIONAL CELLS....................... 240
FIGURE 20 – BOUNDARY SCAN ARCHITECTURE ................................................................ 242
FIGURE 21 – TAP CONTROLLER FINITE STATE MACHINE.................................................. 244
FIGURE 22 – UNCHANNELISED RECEIVE LINK TIMING ...................................................... 248
FIGURE 23 – CHANNELISED T1 RECEIVE LINK TIMING ...................................................... 248
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
viii
PMC [ PMC-SIERRA, INC ]
