RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
exists in the FIFO, a request will be made to the RMAC to initiate a PCI write access to
transfer the data to the PCI host. Channel transfer size is measured in 16 byte blocks. The
amount of data transferred and the depth threshold are specified by given setting is:
XFER[2:0] + 1 blocks = 16 * (XFER[2:0] + 1) bytes
XFER[2:0] should be set such that the number of blocks transferred is at least two fewer than
the total allocated to the associated channel. XFER[2:0] reflects the value written until the
completion of a subsequent indirect channel read operation.
OFFSET[1:0]:
The packet byte offset (OFFSET[1:0]) configures the partial packet processor to insert invalid
bytes at the beginning of a packet stored in the channel FIFO. The value of OFFSET[1:0] to
be written to the channel provision RAM, in an indirect channel write operation, must be set up
in this register before triggering the write. The number of bytes inserted before the beginning
of a HDLC packet is defined by the binary value of OFFSET[1:0]. OFFSET[1:0] reflects the
value written until the completion of a subsequent indirect channel read operation.
INVERT:
The HDLC data inversion bit (INVERT) configures the HDLC processor to logically invert the
incoming HDLC stream from the RCAS before processing it. The value of INVERT to be
written to the channel provision RAM, in an indirect channel write operation, must be set up in
this register before triggering the write. When INVERT is set to one, the HDLC stream is
logically inverted before processing. When INVERT is set to zero, the HDLC stream is not
inverted before processing. INVERT reflects the value written until the completion of a
subsequent indirect channel read operation.
PRIORITY:
The channel FIFO priority bit (PRIORITY) informs the partial packet processor that the
channel has precedence over other channels when being serviced by the RMAC block for
transfer to the PCI host. The value of PRIORITY to be written to the channel provision RAM,
in an indirect channel write operation, must be set up in this register before triggering the
write. Channel FIFOs with PRIORITY set to one are serviced by the RMAC before channel
FIFOs with PRIORITY set to zero. Channels with an HDLC data rate to FIFO size ratio that is
significantly higher than other channels should have PRIORITY set to one. PRIORITY
reflects the value written until the completion of a subsequent indirect channel read operation.
7BIT:
The 7BIT enable bit (7BIT) configures the HDLC processor to ignore the least significant bit of
each octet in the corresponding link RD[n]. The value of 7BIT to be written to the channel
provision RAM, in an indirect channel write operation, must be set up in this register before
triggering the write. When 7BIT is set high, the least significant bit (last bit of each octet
received), is ignored. When 7BIT is set low, the entire receive data stream is processed.
7BIT reflects the value written until the completion of a subsequent indirect channel read
operation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
123
PMC [ PMC-SIERRA, INC ]
