RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
Register 0x208 : RHDL Indirect Channel Data Register #2
Bit
Type
Function
Default
Bit 31 to
Bit 16
Unused
XXXXH
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
R/W
R/W
R/W
7BIT
PRIORITY
INVERT
Unused
0
0
0
X
X
X
0
Unused
Unused
R/W
R/W
OFFSET[1]
OFFSET[0]
Unused
Bit 8
0
Bit 7
X
X
X
X
X
X
0
Bit 6
Unused
Bit 5
Unused
Bit 4
Unused[
Unused
Bit 3
Bit 2
R/W
R/W
R/W
XFER[2]
XFER[1]
XFER[0]
Bit 1
Bit 0
0
This register contains data read from the channel provision RAM after an indirect read operation
or data to be inserted into the channel provision RAM in an indirect write operation.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register.
Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all
four byte enables are negated, no access is made to this register.
XFER[2:0]:
The indirect channel transfer size (XFER[2:0]) configures the amount of data transferred in
each transaction. The channel transfer size to be written to the channel provision RAM, in an
indirect write operation, must be set up in this register before triggering the write. When the
channel FIFO depth reaches the depth specified by XFER[2:0] or when an end-of-packet
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
122
PMC [ PMC-SIERRA, INC ]
