RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
Fig. 14 Microprocessor Interface Read Timing
A[8:0]
Valid Address
tS
tH
ALR
ALR
tV
L
tS
tH
LR
LR
ALE
tS
tH
AR
AR
(CSB+RDB)
tZ
tZ
INTH
RD
tP
RD
D[7:0]
Valid Data
Notes on Microprocessor Interface Read Timing:
1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt
point.
2. Maximum output propagation delays are measured with a 100 pF load on the
Microprocessor Interface data bus, (D[7:0]).
3. A valid read cycle is defined as a logical OR of the CSB and the RDB signals.
4. In non-multiplexed address/data bus architectures, ALE should be held high so
parameters tS
, tH , tV , and tS are not applicable.
ALR ALR L LR
5. Parameter tH
is not applicable if address latching is used.
AR
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
153
PMC [ PMC-SIERRA, INC ]
