RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
Ball
Ball
Name
Type
No. Function
High Speed LVDS Links
LRXC[15]
LRXC[14]
LRXC[13]
LRXC[12]
LRXC[11]
LRXC[10]
LRXC[9]
LRXC[8]
LRXC[7]
LRXC[6]
LRXC[5]
LRXC[4]
LRXC[3]
LRXC[2]
LRXC[1]
LRXC[0]
Input
A5 The low-speed receive clock (LRXC[15:0]) inputs
C4 provide timing for the receive links. Each LRXC
A3 signal is independent of the others.
(SCIANY
= 0)
D3
Each signal in LRXD[15:0] is sampled either on the
E4
rising or the falling edge of the corresponding
J4
LRXC[15:0] clock, depending the value of the
K2
LRXCINV bit of the Master Configuration register.
M1
By default, the rising edge is used.
N4
The active edge on each LRXC must only occur
during those bit periods containing ATM cell data. It
must be suppressed during bit periods containing
transmission overhead. These inputs are only
active if the SCIANY input is a logic low.
L5
N5
N7
P8
N8
N9
P11
Maximum clock rate is 50 MHz.
LTXD[15]
LTXD[14]
LTXD[13]
LTXD[12]
LTXD[11]
LTXD[10]
LTXD[9]
LTXD[8]
LTXD[7]
LTXD[6]
LTXD[5]
LTXD[4]
LTXD[3]
LTXD[2]
LTXD[1]
LTXD[0]
Output
A6 The low-speed transmit data signals (LTXD[15:0])
C6 carry the outgoing link data in bit serial format.
B2 Each LTXD signal is independent of the other
C2 signals. The most significant bit of each data byte is
D1 transmitted first.
F2
Each signal in LTXD[15:0] can be updated either on
G1
the rising or falling edge of the corresponding
G4
LTXC[15:0] clock, depending the value of the
G3
LTXCINV bit of the Master Configuration register.
H2
By default, the rising edge is used.
J1
These outputs are only active if the SCIANY input is
a logic low.
P4
N1
M5
When SCIANY is logic high, LTXD[3] and LTXD[0]
become inputs and need to be tied to VDD or VSS
through a pull up or a pull down.
M11
N12
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
18
PMC [ PMC-SIERRA, INC ]
