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PM7350-PI 参数 Datasheet PDF下载

PM7350-PI图片预览
型号: PM7350-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 双串行链路物理层复用器 [DUAL SERIAL LINK PHY MULTIPLEXER]
分类和应用: 复用器ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
文件页数/大小: 241 页 / 1939 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM7350 S/UNI-DUPLEX  
DATA SHEET  
PMC-1980581  
ISSUE 5  
DUAL SERIAL LINK PHY MULTIPLEXER  
Table 22 LVDS Link 61 Byte Cell Configurations  
Far-End  
Near-End  
Resultant Cell contents at far-end Bus or Microprocessor  
input  
Reg  
output  
LVDS: both ends must match e.g. Reg 0x40, 0x50 and 0x60  
Reg 0x14  
0x0C  
S
C
I
H
5
P
S
C
I
H
5
I
P
R
E
L
DEFAULT CONFIGURATION  
R
E
L
N
A
D
D
U
D
F
5 system, 2 prepend, 6 header and 48 data bytes  
U
D
F
U
D
F
USRHDR:  
PREPEND:  
CELLCRC:  
6
1
0
A
N
Y
A
N
Y
E
N
[1  
..  
E
N
[1  
..  
Control cell prepend bytes 2&3 and header bytes 8&9 are  
valid at far-end microprocessor.  
0]  
0]  
1
1
2
1
1
0
1
NEAR-END IBUS8=1, FAR-END OBUS8=1  
Cells are transferred from a 54/54/55(XX/XX/XX) byte  
bus to a 54/55/55(XX/XX/XX) byte bus.  
Prepend and H5 bytes are valid.  
NEAR-END IBUS8=1, FAR-END OBUS8=0  
Cells are transferred from a 54/54/55(XX/XX/XX) byte  
bus to a XX/XX/XX(56/58/58) byte bus.  
Prepend MSB and H5 bytes are valid. Prepend LSB and  
UDF bytes are undefined.  
NEAR-END IBUS8=0, FAR-END OBUS8=1  
Cells are transferred from a XX/XX/XX(56/56/58) byte  
bus to a 54/55/55(XX/XX/XX) byte bus.  
Prepend and H5 bytes are valid.  
NEAR-END IBUS8=0, FAR-END OBUS8=0  
Cells are transferred from a XX/XX/XX(56/56/58) byte  
bus to a XX/XX/XX(56/56/58) byte bus.  
Prepends and H5/UDF bytes are valid.  
THIS CONFIGURATION IS VALID ONLY IF NEAR-END  
IBUS8=0 AND THE FAR-END OBUS8=1  
Cells are transferred from a 55/55/56(XX/XX/XX) byte  
bus to a 55/56/56(XX/XX/XX) byte bus.  
Prepend (2 bytes) and H5 bytes are valid.  
THIS CONFIGURATION IS VALID ONLY IF NEAR-END  
IBUS8=1  
1
1
1
1
2
2
1
1
1
1
0
0
2
1
Cells are transferred from a 55/55/56(XX/XX/XX) byte  
bus to a 54/55/55(56/58/58) byte bus.  
Prepend (2 bytes) and H5 bytes are valid. UDF  
undefined if used.  
1
1
1
1
1
0
2
THIS CONFIGURATION IS VALID ONLY IF NEAR-END  
OBUS8=1  
Cells are transferred from a 54/54/55(56/56/58) byte bus  
to a 55/56/56(XX/XX/XX) byte bus.  
Prepend (2 bytes) and H5 bytes are valid.  
Table 23 LVDS Link 59 Byte Cell Configurations with CRC  
Far-End  
Near-End  
Resultant Cell contents at far-end Bus or Microprocessor  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
192  
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