RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
12
OPERATION.........................................................................................184
12.1 MICROPROCESSOR INBAND COMMUNICATION..................184
12.2 INTERACTION BETWEEN BUS AND LVDS
CONFIGURATIONS...................................................................186
12.3 MAXIMUM CELL BIT RATE .......................................................195
12.4 MINIMUM PROGRAMMING......................................................196
12.5 JTAG SUPPORT........................................................................198
FUNCTIONAL TIMING..........................................................................205
13.1 SCI-PHY/ANY-PHY INTERFACE...............................................205
13.2 CLOCKED SERIAL DATA INTERFACE .....................................210
ABSOLUTE MAXIMUM RATINGS........................................................212
D.C. CHARACTERISTICS....................................................................213
13
14
15
16
MICROPROCESSOR INTERFACE TIMING
CHARACTERISTICS............................................................................217
17
18
19
A.C. TIMING CHARACTERISTICS.......................................................221
ORDERING AND THERMAL INFORMATION.......................................228
MECHANICAL INFORMATION.............................................................230
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
ii
PMC [ PMC-SIERRA, INC ]
