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PM7350-PGI 参数 Datasheet PDF下载

PM7350-PGI图片预览
型号: PM7350-PGI
PDF下载: 下载PDF文件 查看货源
内容描述: [Support Circuit, 1-Func, CMOS, PBGA160, 15 X 15 MM, 1.81 MM HEIGHT, PLASTIC, BGA-160]
分类和应用: ATM异步传输模式电信电信集成电路
文件页数/大小: 245 页 / 898 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM7350 S/UNI DUPLEX  
DATA SHEET  
PMC-1980581  
ISSUE 8  
DUAL SERIAL LINK PHY MULTIPLEXER  
Register 0x2D: Microprocessor Cell Data  
Bit  
Type  
Function  
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
MCDAT[7]  
MCDAT[6]  
MCDAT[5]  
MCDAT[4]  
MCDAT[3]  
MCDAT[2]  
MCDAT[1]  
MCDAT[0]  
X
X
X
X
X
X
X
X
MCDAT[7:0]:  
The MCDAT[7:0] is used to write to the Insert FIFO or read from the selected  
Extract FIFO by the microprocessor.  
When inserting cells, the Insert FIFO Ready register may be polled to  
determine whether the FIFO is ready to receive a cell. Alternately, an  
interrupt may be generated by setting the Insert FIFO Interrupt Enable  
register bit accordingly. A cell is transferred to the Insert FIFO by performing  
successive write accesses to the Microprocessor Cell Data register. The rising  
edge of WRB for two successive write accesses to this register must  
separated by at least three REFCLK periods.  
When extracting cells, the Extract FIFO Ready register may be polled to  
determine which FIFO has a cell available to be read. Alternately, an  
interrupt may be generated by setting the Extract FIFO Interrupt Enable  
register bit accordingly. Selection of the Extract FIFO is done by writing the  
EXTFSEL bit of the Extract FIFO Control register. A cell is transferred from an  
Extract FIFO by performing successive read accesses to the Microprocessor  
Cell Data register. The falling edge of RDB for two successive read accesses  
to this register must separated by at least three REFCLK periods.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
132  
 
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