S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
Similarly, the first stuff cell insertion on the previous TRL occurs in approximately the same
frame a stuff cell would have been inserted had it still been the TRL although the actual frame
for stuff insertion will also be dependent on the rate difference with the new TRL. This
minimizes any effects on the differential delay for the group as well as reducing any FIFO level
changes. All subsequent stuff cell insertions on the TRL then happen after every 2048 cells and
all subsequent stuff cell insertions on the former TRL are dependent only on the link’s rate
difference from the new TRL.
10.2.4 Receive IMA Data Processor (RDAT)
The Receive IMA Data Processor (RDAT) performs the IMA data-flow functions in the receive
direction including the IMA Frame Synchronization Mechanism (IFSM), storage of data for
accommodating differential delay, defect detection, and playout of data in a round robin fashion.
One 16 Mbit (1 Mbit x 16) SDRAM, available as a single chip device, is required. Differential-
delay tolerance may be configured through registers on a per-group basis to any value up to the
maximum listed in Figure 11. Buffering is allocated on a per link basis. Each link is allocated
the same number of cell buffers. Each link is allocated 1024 cell buffers. See Figure 11 for the
required memory sizes.
Figure 11 Max Differential Delay Tolerance
# of T1/E1
Links
4 T1/ 4 E1
Cells of
B uffering in m s
1024 282 m s
Delay (T1) Delay (E 1) in S DRAM
m s
size
226 m s 1M bit x16
Writing data to the Delay Compensation Buffers (DCB)
When there is a full cell of data in the RX Link FIFOs, the link requests service. The RDAT
arbitrates between links requiring service in a round-robin fashion.
When a link is chosen for service, if it is not an IMA link, the cells are stored in external
memory in a per link FIFO.
For IMA links, the IFSM is performed to locate the IMA Frame. Once the IMA frame is located,
the RDAT calculates the location to store the cells. The cells are stored in a time-based FIFO
structure. The buffer address for a cell is created from the cell number in the IMA frame
concatenated with the lower x (depends upon M) bits of the IMA frame sequence number. Each
link has its own reserved FIFO. The cells are stored in this manner such that they are aligned in
time in the external memory and the differential-delay removal is simplified.
During periods in which the link is in a defect state, incoming cells will be replaced with filler
cells prior to being written to the DCB.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
57
PMC [ PMC-SIERRA, INC ]
