S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
11.11 RX IDCC Registers
Register 0x350: RXIDCC Indirect Link Control Register
Bit
15
Type
R
Function
CBUSY
Default
0
14
R/W
N/A
R/W
N/A
R/W
LRWB
Unused
LSEL[1:0]
Unused
LADDR[1:0]
0
N/A
0
N/A
0
13:9
8:7
6:2
1:0
Writing to this register triggers an indirect channel register access.
LADDR [1:0]:
The indirect link address number (LADDR [1:0]) indicates the link to be configured or
interrogated in the indirect link access.
LSEL
LSEL selects the RAM to interrogate or configure.
00 – Unused
01 – Link Table
10 – Reserved
11 – Reserved
LRWB
The link indirect access control bit (LRWB) selects between a configure (write) or
interrogate (read) access to the RAM. Writing logic 0 to LRWB triggers an indirect write
operation. Data to be written is taken from the Indirect Link Data registers. Writing logic 1
to LRWB triggers an indirect read operation.
CBUSY
The indirect access command bit (CBUSY) reports the progress of an indirect access.
CBUSY is set high to trigger an indirect access, and will stay high until the access is
complete. Once the access is complete, the CBUSY signal is reset by the device. This
register should be polled to determine when data from an indirect read operation is available
in the Indirect Data register or to determine when a new indirect write operation may
commence.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
250
PMC [ PMC-SIERRA, INC ]
