S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
Register 0x328: Transmit Link FIFO Overrun Interrupt Register
Bit
15:4
3:0
Type
R
R2C
Function
Reserved
Link_FIFO_OVERFLOW_STAT [3:0]
Default
0
0
The Transmit Link FIFO Overrun Interrupt register reports an overrun on the TTC Link FIFOs,
which occurs when a write is attempted to a full FIFO. If an overrun occurs during the same
cycle as a read, the set of an interrupt bit overrides the clear operation.
Programming errors such as duplicate mapping of multiple LIDs to the same link FIFO can
cause link FIFO overflows. In addition, many changes of group transmit TRL LID may cause
overflows (as slight rate inaccuracies can accumulate during these operations). Overflows
should never occur under normal operation, however, if they do occur then a single cell will be
dropped. Afterwards, the FIFO will behave normally.
Link FIFO Overflow Status[3:0]
On read, each bit reports the status of the corresponding link FIFO
(1= overflow, 0 = no overflow).
Each set overflow status bit is cleared after a read.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
246
PMC [ PMC-SIERRA, INC ]
