S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
11.9 TIMA registers
Register 0x320: TIMA Indirect Memory Command
Bit
15
14
13:3
2:0
Type
R
R/W
Function
MEM_BUSY
MEM_RWB
Unused
Default
0
0
0
0
R/W
MEM_SELECT
Writing to this register triggers an indirect memory access to the TIMA Context tables. The
indirect memory address (and data register for write operations) must be configured prior to
writing this register.
MEM_SELECT
The indirect memory select indicates the memory table (or register bank) within the TIMA
that will be accessed.
MEM_SELECT
TIMA Memory
Transmit IMA Group Context Table
Transmit IMA Group Configuration Table 0x2A0-0x2A3
Address Range
0x000-0x03F
0
0
1
Transmit LID to Physical Link Mapping
0x000-0x07F
Table
2
3-7
Transmit Physical Link Context Table
Reserved
0x000-0x007
MEM_RWB
The memory indirect access control bit (MEM_RWB) selects between a configure (write)
or interrogate (read) access to the TIMA internal. Writing a logic 0 to MEM_RWB triggers
an indirect write operation. Data to be written is taken from the Indirect Memory Data
registers. Writing a logic 1 to MEM_RWB triggers an indirect read operation. The read data
can be found in the Indirect Memory Data registers. The address within a memory table can
be found in the Indirect Memory Address register.
MEM_BUSY
The indirect memory access status bit (MEM_BUSY) reports the progress of an indirect
access. A write to the Indirect Memory Command register triggers an indirect access and
sets MEM_BUSY to a logic 1; MEM_BUSY will remain logic 1 until the access is
complete. This register should be polled to determine when data from an indirect read
operation is available in the TIMA Indirect Memory Data registers or to determine when a
new indirect write operation may commence.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
235
PMC [ PMC-SIERRA, INC ]
