S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
MEM_BUSY
The indirect memory access status bit (MEM_BUSY) reports the progress of an indirect
access A write to the Indirect Memory Command register triggers an indirect access and
sets the MEM_BUSY bit to a logic 1, MEM_BUSY will remain logic 1 until the access is
complete. This register should be polled to determine either: (1) when data from an indirect
read operation is available in the Indirect Memory Data registers or (2) when a new indirect
write operation may commence.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
210
PMC [ PMC-SIERRA, INC ]
