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PM7348 参数 Datasheet PDF下载

PM7348图片预览
型号: PM7348
PDF下载: 下载PDF文件 查看货源
内容描述: [ATM/SONET/SDH IC, CMOS, PBGA324,]
分类和应用: ATM异步传输模式
文件页数/大小: 318 页 / 1736 K
品牌: PMC [ PMC-SIERRA, INC ]
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S/UNI-IMA-4 Telecom Standard Product Data Sheet  
Released  
Figure 33 Layout of Output Enable and Bi-directional Cells ................................................... 267  
Figure 34 Unchannelized Receive Link Timing....................................................................... 293  
Figure 35 Channelized T1 Receive Link Timing ..................................................................... 293  
Figure 36 Channelized E1 Receive Link Timing ..................................................................... 294  
Figure 37 Unchannelized Transmit Link Timing...................................................................... 294  
Figure 38 Channelized T1 Transmit Link Timing w/ Clock gapped Low................................. 295  
Figure 39 Channelized T1 Transmit Link Timing w/ Clock gapped high................................. 295  
Figure 40 Channelized E1 Transmit Link Timing w/ Clock gapped Low................................. 296  
Figure 41 Channelized E1 Transmit Link Timing w/ Clock gapped High................................ 296  
Figure 42 UTOPIA L2 Transmit Slave..................................................................................... 297  
Figure 43 Any-PHY Transmit Slave ........................................................................................ 297  
Figure 44 UTOPIA L2 Multi-PHY Receive Slave .................................................................... 298  
Figure 45 UTOPIA L2 Single-PHY Receive Slave.................................................................. 299  
Figure 46 Any-PHY Receive Slave ......................................................................................... 299  
Figure 47 SDRAM Read Timing.............................................................................................. 300  
Figure 48 SDRAM Write Timing.............................................................................................. 301  
Figure 49 SDRAM Refresh...................................................................................................... 301  
Figure 50 Power Up and Initialization Sequence .................................................................... 302  
Figure 51 Microprocessor Interface Read Timing................................................................... 307  
Figure 52 Microprocessor Interface Write Timing ................................................................... 308  
Figure 53 RSTB Timing........................................................................................................... 309  
Figure 54 Synchronous I/O Timing.......................................................................................... 309  
Figure 55 JTAG Port Interface Timing..................................................................................... 314  
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.  
Document No.: PMC-2020889, Issue 2  
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