Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
8.4.2.2 TX_SC_STATE (Internal Structure)
Offset: 1h (4h byte)
Type: Read/Write – Do not write while SW_RESET (refer to “SW_RESET” on
page 101) is deasserted.
Format: Refer to the following table.
Field (Bits)
Description
RAM is not present in these bit locations.
Not present
(31:16)
TX_SC_CONG_ST
(15)
Congestion state bit for the SC congestion determination. Initialize to 0. This bit is read-
only while cells are flowing.
TX_SC_CUR_QD
(14:0)
Current SCQ depth. This is the count of the cells queued in all SC N across the VOs. Ini-
tialize to 0000h. This field is maintained by a state machine and is read-only after initial-
ization.
8.4.3 Transmit Multicast SC Control Block Summary
Base address: 1200C0h (480300h byte)
Index: 4h
Number of entries: 8 (64 words)
Type: Read/Write – Do not write while SW_RESET (refer to “SW_RESET” on
page 101) is deasserted.
Long address = 200C0 + 8 × (service_class mod 8) + offset
h
h
Byte address = 480300 + 20 × (service_class mod 8) + offset
h
h
Table 30. Transmit Multicast SC Control Block Summary
Byte
Offset Offset
Long
Read or
Write
Name
Description
0h
4h
8h
Ch
0h
1h
2h
3h
TX_SC_MC_IN_FIFO_HEAD
TX_SC_MC_IN_FIFO_TAIL
TX_SC_MC_BOTTLE
R/W
R/W
R/W
R/W
Head of the multicast input FIFO for this SC.
Tail of the multicast input FIFO for this SC.
Bottlenecked VO for multicast in this SC.
TX_SC_MC_NEXT_HEADER_PTR
The next multicast linked list entry (refer to sec-
tion “MC_LIST” on page 195) to be transferred
into an SCQ output FIFO.
10-1Ch
4-7h
Reserved
R/W
Initialize to 0 at initial setup. Software modifi-
cations to this location after setup may cause
incorrect operation.
164
PMC [ PMC-SIERRA, INC ]
