Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
NOTES:
•
All bits marked “Reserved” must be initialized to 0 (unless otherwise indicated) at initial setup. Soft-
ware modifications to these locations after setup may cause incorrect operation.
•
•
All read/write bits marked “Not used” must be written with the value 0 to maintain software compatibil-
ity with future versions.
Most read-only bits marked “Not used” are driven with a 0; however, some may have an unpredictable
value on reads. Therefore, all read-only bits marked “Not used” should be masked by the software on
reads to maintain compatibility with future versions.
•
RAM is not present in bit locations marked “Not present”.
8.2 Transmit Service Class RAM (TSC_RAM) Summary
The TSC_RAM contains the Transmit Service Class Queue (TX SCQ) control block. Figure 67
shows a memory map of the TSC_RAM.
D15
D0
100000h
TX SCQ Control
Block(0)
VO = 0 SC = 0
100003h
100004h
TX SCQ
Control Block(1)
VO = 0 SC = 1
100007h
100008h
TX SCQ Control Block
•
•
•
1007B8h
1007B9h
TX SCQ
Control Block(495)
VO = 30 SC = 15
1007BFh
1007C0h
Not Used
Not Used
1009FFh
Figure 67. Transmit Service Class RAM (TSC_RAM) Memory Map
151
PMC [ PMC-SIERRA, INC ]
