Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
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Provides two 100 MHz, 32-bit, synchronous DRAM cell buffer interfaces.
Provides three 100 MHz, synchronous SRAM control interfaces.
Provides a JTAG boundary scan interface.
COMPATIBILITY FEATURES
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Compatible with the ATM Forum 3.0, 3.1, and 4.0 specifications.
Compatible with the ATM Forum UTOPIA Level 1 and Level 2 specifications.
Compatible with the PM73488 ATM QSE.
PHYSICAL CHARACTERISTICS
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3.3 V supply voltage.
5 V tolerant inputs on the microprocessor and UTOPIA interfaces.
Available in a 503-pin Enhanced Plastic Ball Grid Array (EPBGA) package.
BLOCK DIAGRAM
Figure 1 shows a QRT system block diagram.
Receive Cell SDRAM
622 Mbps ATM
Traffic Mgt Device
(QRT)
To Switch Fabric
Receive UTOPIA
Host Interface
Control SSRAM
Transmit UTOPIA
PM73487
From Switch Fabric
Transmit Cell SDRAM
Figure 1. QRT System Block Diagram
3
PMC [ PMC-SIERRA, INC ]
