S/UNI®-JET Data Sheet
Released
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Maintaining the transmit FIFO read and write pointers.
Detecting a FIFO overrun condition.
The FIFO interface is “UTOPIA Level 2” compliant and accepts a write clock (TFCLK), a write
enable signal (TENB), the start of a cell (TSOC) indication, and the parity bit (TPRTY), and the
ATM device address (TADR[4:0]) when data is written to the transmit FIFO (using the rising
edges of TFCLK). The interface provides the transmit cell available status (TCA and
DTCA[4:1]), which can transition from "available" to "unavailable" when the transmit FIFO is
near full (when TCALEVEL0 is logic zero) or when the FIFO is full (when TCALEVEL0 is logic
one) and can accept no more writes. To reduce FIFO latency, the FIFO depth at which TCA and
DTCA[x] indicates "full" can be set to one, two, three, or four cells by the FIFODP[1:0] bits of
TXCP-50 Configuration 2 Register. If the programmed depth is less than four, more than one cell
may be written after TCA or DTCA[x] is asserted as the TXCP-50 still allows four cells to be
stored in its FIFO. This interface also indicates FIFO overruns via a maskable interrupt and
register bit, but write accesses while TCA or DTCA[x] is logic zero are not processed. The TXFF
automatically transmits idle cells until a full cell is available to be transmitted.
10.21 TTB Trail Trace Buffer
The Trail Trace Buffer (TTB) extracts and sources the trail trace message carried in the TR byte
of the G.832 E3 stream. The message is used by the OS to prevent delivery of traffic from the
wrong source and is 16 bytes in length.
The 16-byte message is framed by the PTI Multiframe Alignment Signal (TMFAS = 'b10000000
00000000). One bit of the TMFAS is placed in the most significant bit of each message byte. In
the receive direction, the trail trace message is extracted from the serial overhead stream output
by the E3-FRMR. The extracted message is stored in the internal RAM for review by an external
microprocessor. By default, the TTB will write the byte of a 16-byte message with its most
significant bit set high to the first location in the RAM. The extracted trail trace message is
checked for consistency between consecutive multiframes. A message received unchanged three
or five times (programmable) is accepted for comparison with the copy previously written into
the internal RAM by the external microprocessor. Alarms are raised to indicate reception of
unstable and mismatched messages. In the transmit direction, the TTB sources the trail trace
message from the internal RAM for insertion into the TR byte by the E3-TRAN.
The TTB also extracts the Payload Type label carried in the MA byte of the G.832 E3 stream. The
label is used to ensure that the adaptation function at the trail termination sink is compatible with
the adaptation function at the trail termination source. The Payload Type label is check for
consistency between consecutive multiframes. A Payload Type label received unchanged for five
frames is accepted for comparison with the copy previously written into the TTB by the external
microprocessor. Alarms are raised to indicate reception of unstable and mismatched Payload Type
label bits.
10.22 JTAG Test Access Port
The JTAG Test Access Port block provides JTAG support for boundary scan. The standard JTAG
EXTEST, SAMPLE, BYPASS, IDCODE, and STCTEST instructions are supported.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
75
PMC [ PMC-SIERRA, INC ]
