S/UNI®-JET Data Sheet
Released
14 Functional Timing
All functional timing diagrams assume that polarity control is not being applied to input and
output data and clock lines (i.e. polarity control bits in the S/UNI-JET registers are set to their
default states).
Figure 29 Receive DS1 Stream
RCLK
F BIT
INFO 1
INFO 2
INFO 3
INFO 192
F BIT
INFO 1 INFO 2
INFO 3 INFO 4
INFO 5
INFO 4
RDATI
ROHM
The Receive DS1 Stream diagram (Figure 29) shows the expected DS1 overhead indicators on
ROHM when the S/UNI-JET is configured for DS1 PLCP or DS1 direct-mapped frame formats.
Frame pulses on ROHM are not required to be present. Once internally synchronized by a pulse
on ROHM, the S/UNI-JET can use its internal timeslot counter for DS1 overhead bit
identification. The ATM cell stream is contained in RDATI, along with a framing bit placeholder
every 193 bit periods. An upstream DS1 framer (such as the PM4341A T1XC or PM4344
TQUAD) must be used to identify the DS1 framing bit position.
Figure 30 Receive E1 Stream
RCLK
TS0 bit1 TS0 bit2 TS0 bit3 TS0 bit4
TS31 bit8 TS0 bit1 TS0 bit2 TS0 bit3 TS0 bit4 TS0 bit5 TS0 bit6
TS0 bit5
RDATI
ROHM
The expected Receive E1 Stream for direct-mapped or PLCP applications is shown in Figure 30.
Frame pulses on ROHM are not required to be present every frame. Once internally synchronized
by a pulse on ROHM, the S/UNI-JET can use its internal timeslot counter for E1 overhead bit
identification. The ATM cell stream is contained in RDATI, along with a framing bit placeholder
every 256 bit periods. An upstream E1 framer (such as the PM6341A E1XC or PM6344 EQUAD)
must be used to identify the E1 framing bit position.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
295
PMC [ PMC-SIERRA, INC ]
