S/UNI®-JET Data Sheet
Released
Register 330H: DS3 FRMR Configuration
Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
AISPAT
FDET
MBDIS
M3O8
UNI
REFR
AISC
CBE
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
0
0
0
0
0
0
CBE
The CBE bit enables the DS3 C-bit parity application. When a logic one is written to CBE, C-
bit parity mode is enabled. When a logic zero is written to CBE, the DS3 M23 format is
selected. While the C-bit parity application is enabled, C-bit parity error events, FEBEs are
accumulated.
AISC
The AISC bit controls the algorithm used to detect the AIS (AIS). When a logic one is written
to AISC, the algorithm checks that a framed DS3 signal with all C-bits set to logic zero is
observed for a period of time before declaring AIS. The payload contents are checked to the
pattern selected by the AISPAT bit. When a logic zero is written to AISC, the AIS detection
algorithm is determined solely by the settings of AISPAT and AISONES register bits (see bit
mapping table in the Additional Configuration Register description).
REFR
The REFR bit initiates a DS3 reframe. When a logic one is written to REFR, the S/UNI-JET
is forced OOF, and a new search for frame alignment is initiated. Note: Only a low-to-high
transition of the REFR bit triggers reframing; multiple write operations are required to ensure
such a transition.
UNI
The UNI bit configures the S/UNI-JET to accept either dual-rail or single-rail receive DS3
streams. When a logic one is written to UNI, the S/UNI-JET accepts a single-rail DS3 stream
on RDATI. The S/UNI-JET accumulates LCV on the RLCV input. When a logic zero is
written to UNI, the S/UNI-JET accepts B3ZS-encoded dual-rail data on RPOS and RNEG.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
126
PMC [ PMC-SIERRA, INC ]
