PM7346 S/UNI-QJET
DATASHEET
PMC-960835
ISSUE 6
SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Pin Name
Type
Input
Pin No. Function
TFCLK
E20
Transmit FIFO Write Clock (TFCLK). This
signal is used to write ATM cells to the four
cell transmit FIFOs. TFCLK cycles at a 52
MHz or lower instantaneous rate.
Please note that the TFCLK input is not 5
V tolerant, it is a 3.3 V only input pin.
DTCA[4]
DTCA[3]
DTCA[2]
DTCA[1]
Output J17
Direct Access Transmit Cell Available
(DTCA[4:1]). These output signals
J18
J19
K19
indicate when a cell is available in the
transmit FIFO for the corresponding port.
When high, DTCA[x] indicates that the
corresponding transmit FIFO is not full and
a complete cell may be written. DTCA[x]
can be configured to indicate either that
the corresponding transmit FIFO is near
full and can accept no more than four
writes or that the corresponding transmit
FIFO is full. DTCA[x] will thus transition
low on the rising edge of TFLCK which
samples Payload byte 43 (TCALEVEL0=0)
or 47 (TCALEVEL0=1) for the 8-bit
interface (ATM8=1), or the rising edge of
TFCLK which samples Payload word 19
(TCALEVEL0=0) or 23 (TCALEVEL0=1)
for the 16-bit interface (ATM8=0). To
reduce FIFO latency, the FIFO depth at
which DTCA[x] indicates "full" can be set
to one, two, three or four cells. Note that
regardless of what fill level DTCA[x] is set
to indicate "full" at, the transmit cell
processor can store 4 complete cells.
The polarity of DTCA[x] (with respect the
the description above) is inverted when
the TCAINV register bit is set to logic 1.
The DTCA[4:1] outputs can be used to
support Utopia Direct Access mode.
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE 45
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