欢迎访问ic37.com |
会员登录 免费注册
发布采购

PM7346 参数 Datasheet PDF下载

PM7346图片预览
型号: PM7346
PDF下载: 下载PDF文件 查看货源
内容描述: SATURN QUAD用户网络接口, J2 , E3 , T3 [SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3]
分类和应用: 网络接口
文件页数/大小: 419 页 / 2502 K
品牌: PMC [ PMC-SIERRA, INC ]
 浏览型号PM7346的Datasheet PDF文件第21页浏览型号PM7346的Datasheet PDF文件第22页浏览型号PM7346的Datasheet PDF文件第23页浏览型号PM7346的Datasheet PDF文件第24页浏览型号PM7346的Datasheet PDF文件第26页浏览型号PM7346的Datasheet PDF文件第27页浏览型号PM7346的Datasheet PDF文件第28页浏览型号PM7346的Datasheet PDF文件第29页  
PM7346 S/UNI-QJET  
DATASHEET  
PMC-960835  
ISSUE 6  
SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3  
32  
Provides programmable pseudo-random test-sequence detection (up to 2  
1 bit length patterns conforming to ITU-T O.151 standards) and analysis  
features.  
-
The transmitter section:  
Provides frame insertion for the M23 or C-bit parity DS3 applications, alarm  
insertion, and diagnostic features. In addition, far end alarm channel codes  
may be inserted, and an integral HDLC transmitter is provided to insert the  
path maintenance data link.  
Provides frame insertion for the G.751 or G.832 E3 applications, alarm  
insertion, and diagnostic features. In addition, for G.832, the Trail Trace is  
inserted, and an integral HDLC transmitter is provided to insert either the  
Network Requirement or the General Purpose data link.  
Provides frame insertion for G.704 6.312 Mbit/s J2 applications, alarm  
insertion, and diagnostic features. An integral HDLC transmitter is provided  
to insert the path maintenance data link.  
Provides frame insertion and path overhead insertion for DS1, DS3, E1 or E3  
based PLCP formats. In addition, alarm insertion and diagnostic features are  
provided.  
Provides a 50 MHz 8-bit wide or 16-bit wide Utopia FIFO buffer in the transmit  
path with parity support and multi-PHY (Level 2) control signals.  
Provides optional ATM cell scrambling, header scrambling (for use with PPP  
packets), HCS generation/insertion, programmable idle cell insertion,  
diagnostics features and accumulates transmitted cells read from the FIFO.  
Provides a four cell FIFO for rate decoupling between the line and a higher  
layer processing entity. FIFO latency may be reduced by changing the  
number of operational cell FIFOs.  
Provides a transmit HDLC controller with a 128-byte FIFO.  
Provides an 8 kHz reference input for locking the transmit PLCP frame rate to  
an externally applied frame reference.  
Provides programmable pseudo-random test sequence generation (up to  
32  
2
-1 bit length sequences conforming to ITU-T O.151 standards).  
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE 4  
 复制成功!